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| Autumn 2019 Semester. 2h Lectures, 2h Exercises, 2h Labs. Continuous Control | Autumn 2019 Semester. 2h Lectures, 2h Exercises, 2h Labs. Continuous Control | ||
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| + | Instructors: [[http://lara.epfl.ch/~kuncak/|Viktor Kuncak]] and [[https://people.epfl.ch/jad.hamza?lang=en|Jad Hamza]] | ||
| ===== Introduction ===== | ===== Introduction ===== | ||
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| ===== Topics ===== | ===== Topics ===== | ||
| - | Importance of Reliable Systems. Methodology of Formal Verification. Soundness and Completeness in Modeling and Tools. Successful Tools and Flagship Case Studies | + | * Importance of Reliable Systems. Methodology of Formal Verification. Soundness and Completeness in Modeling and Tools. Successful Tools and Flagship Case Studies |
| - | + | * Review of Sets, Relations, Computability, Propositional and First-Order Logic Syntax, Semantics, Sequent Calculus. | |
| - | Review of Sets, Relations, Computability, Propositional and First-Order Logic Syntax, Semantics, Sequent Calculus. | + | * Completeness and Semi-Decidability for First-Order Logic. Inductive Definitions and Proof Trees. Higher-Order Logic and LCF Approach. |
| - | + | * State Machines. Transition Formulas. Traces. Strongest Postconditions and Weakest Preconditions. | |
| - | Completeness and Semi-Decidability for First-Order Logic. Inductive Definitions and Proof Trees. Higher-Order Logic and LCF Approach. | + | * Hoare Logic. Inductive Invariants. Well-Founded Relations and Termination Measures |
| - | + | * Modeling Hardware: Verilog to Sequential Circuits | |
| - | State Machines. Transition Formulas. Traces. Strongest Postconditions and Weakest Preconditions. | + | * Linear Temporal Logic. System Verilog Assertions. Monitors |
| - | + | * SAT Solvers and Bounded Model Checking | |
| - | Hoare Logic. Inductive Invariants. Well-Founded Relations and Termination Measures | + | * Model Checking using Binary Decision Diagrams |
| - | + | * Loop Invariants. Hoare Logic. Statically Checked Function Contracts. Relational Semantics and Fixed-Point Semantics | |
| - | Modeling Hardware: Verilog to Sequential Circuits | + | * Symbolic Execution. Satisfiability Modulo Theories |
| - | + | * Abstract Interpretation and Predicate Abstraction | |
| - | Linear Temporal Logic. System Verilog Assertions. Monitors | + | * Information Flow and Taint Analysis |
| - | + | * Verification of Security Protocols | |
| - | SAT Solvers and Bounded Model Checking | + | * Dependent and Refinement Types |
| - | + | ||
| - | Model Checking using Binary Decision Diagrams | + | |
| - | + | ||
| - | Loop Invariants. Hoare Logic. Statically Checked Function Contracts. Relational Semantics and Fixed-Point Semantics | + | |
| - | + | ||
| - | Symbolic Execution. Satisfiability Modulo Theories | + | |
| - | + | ||
| - | Abstract Interpretation and Predicate Abstraction | + | |
| - | + | ||
| - | Information Flow and Taint Analysis | + | |
| - | + | ||
| - | Verification of Security Protocols | + | |
| - | + | ||
| - | Dependent and Refinement Types | + | |
| ===== Relevant Textbooks ===== | ===== Relevant Textbooks ===== | ||
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| * http://logitext.mit.edu/tutorial | * http://logitext.mit.edu/tutorial | ||
| - | ==== Additional Introductions and Background ==== | + | ===== Additional Introduction and Background ===== |
| * Kenneth H. Rosen. Discrete Mathematics and Its Applications. E.g. 8th Edition. | * Kenneth H. Rosen. Discrete Mathematics and Its Applications. E.g. 8th Edition. | ||
| * Formally Verified Software in the Real World. Communications of the ACM, October 2018. https://cacm.acm.org/magazines/2018/10/231372-formally-verified-software-in-the-real-world/fulltext | * Formally Verified Software in the Real World. Communications of the ACM, October 2018. https://cacm.acm.org/magazines/2018/10/231372-formally-verified-software-in-the-real-world/fulltext | ||